The netlister creates a list of nets by analysing the schematic (the area inside the page border (see the workspace) ). It can also be used to highlight wires associated with the netlist by double clicking in the netlist window (on the netlist data). A flashing highlight in the schematic is shown - useful for checking that the schematic connects wires to the correct symbol pins.
The top panel shows the status of netlisting and the
click the Part to decal (pcb footprint) mapping data lower
down in this list starting from the text
; # mapping
The error panel is not displayed unless an error occurs - to see it disconnect a wire from a pin and re-netlist.
If an error occurs a further panel is displayed showing the error data. You can also click in this window to display the error on the schematic.
The two extra control sets are for more advanced use:
"highlights" and "lock nets for pcb"
Advanced: Lock Nets for pcb
After "Enable" is clicked repeat the netlist action by hitting "Netlist". When you do this netnames are added to the schematic on the specified layer (here layer 7) for each unnamed net.
When you create a PCB it is useful to always use the same netnames because it is easier to identify the same net in the schematic and pcb tool. Lock nets for pcb does this by adding netnames automatically and once they are added the connections will always adopt that netname.
Note the netnames added automatically are exactly the same asnetnames added manualy (they just use a smaller font size (which you can also change manually) so you can go and edit them (just remember to enable layer 7 as selectable and visible in the layer control dialog).Note: Hitting Rem - removes the added netnames
A net is a text description of the connections in the circuit
For the schematic above its netlist is :
NET_ALPHA R1.1 R2.2 R3.1 ;( a single net)
; # mappingR1 RES04
This describes the net (that has been labeled NET_ALPHA in the
schematic) as connecting three components R1, R2 and R3 at pin 1 of R1
and pin 2 of R2 and pin 1 of R3. Note that wires that are not
given a net name are automatically assigned a unique net name during
The mapping uses 'Decal' attribute data to define what
As well as generating the netlist the netlister checks the schematic for errors:
This checks that all pins in the schematic have either a wire connection or overlap another pin. Wires do not have to be used to connect pins - it is sufficient for the pins themselves to overlap - can save space and effort in drawing schematics.
Analysis the netnames and wires to generate the netlist information.
Processing overlapping pins.
Adds the overlapping pins to the netlist information
Processing power pins.
Adds pins defined as global parts generating their netlist data (see options (Global parts) )
Merging and processing net data.
Merges data - can have multiple nets named the same when using netnames to label unconnected wires in the schematic, or when using multiple power pins. Their data is merged into one net i.e. when using a power pins such as VOLT_BAR all the power pins having the same value define the same net i.e. all symbols connected to 5V (say) will all connect to the same 5V net. (see options (Global parts)).
Detecting Single pin nets
If there is only one pin connected to a net then an error is indicated as usually this is an error, however the netlist is still generated as there are cases where this is not an error e.g. an aerial.
Detecting multiple netnames
When netnames are used to label wires all wires must have the same netname - if this is not true then an error is shown (see netnames).
As well as displaying the error in the netlister window the error is also circled within the schematic. Holding the mouse over the error in the schematic will pop up data about the error. To remove all errors from the schematic either use the edit menu control (see the edit menu) or correct the errors and re-netlist.
0V R3.1 R4.1
9V R1.2 R2.2
BASE C1.1 R1.1 R3.2 TR2.2
NET_1 C1.2 IP1.1
NET_2 C2.1 OP1.1
NET_3 C2.2 R2.1 TR2.1
NET_4 R4.2 TR2.3
; # mappingC1 CAP02
Note: The mapping part of the netlist defines the
footprint) of the part. This information is useful for
tool e.g. pcb layout. The decal defines the shape of the pcb
footprint for the component.